DESIGN AND SIMULATION OF BUILDING BLOCKS OF A LOW-DROPOUT VOLTAGE REGULATOR

Low dropout regulators (LDOs) are a simple and inexpensive way to regulate an output voltage that is powered from a higher voltage input [1]. An LDO regulator is a DC linear voltage regulator that can regulate the magnitude of the output voltage even when the supply voltage is very close to the output voltage. In this research paper, various building blocks of a CMOS-based low-dropout voltage regulator were designed and simulated using Multisim LIVE, an online circuit simulator. All of the building blocks were then combined to form the device. Based on the results of the simulation, several spesifications of the LDO were determined. Those are the LDO’s dropout voltage, its quiescent current, its load regulation, and its line regulation. At the end of the design process, during testing it can be shown that this LDO resulted in a dropout voltage of magnitude 200 mV at 200 mA load current which is quite a low dropout voltage. The design has a quiescent current of magnitude 300 μA, a load regulation of magnitude 0.000042 V mA , and a line regulation of magnitude 336.


Introduction
Nearly all electronic circuits, from simple transistor and op-amp circuits up to elaborate digital and microprocessor systems, require one or more sources of stable DC voltage.
Also, there are increasing number of portable applications that need to maintain the required system voltage, independently of the state of battery charge. Not to mention the equipment that needs constant and stable voltage, while minimizing the upstream supply (or working with wide fluctuations in upstream supply). Typical examples include circuitry with digital and RF loads.
In essence, we need a mean to produce voltage with a constant and stable magnitude. Such voltage will be used by various digital and analog circuit and a ranges of application.
A device known as voltage regulator will do this task. A voltage regulator is a system designed to automatically maintain a constant voltage level. One type of voltage regulator are linear regulators, also called series regulators. It is called linear because it linearly modulates the conductance of a series pass switch connected between an input dc supply and the regulated output. While the term "series" refers to the pass element (or switch device) that is in series with the unregulated supply and the load.
There are two types of linear regulators: standard linear regulators or high-dropout linear regulators (HDOs) and low-dropout linear regulators (LDOs). The difference between the two is in the pass element and the amount of dropout voltage required to maintain a regulated output voltage. Dropout voltage refers to the minimum voltage dropped across the circuit, or in other words, the minimum voltage difference between the unregulated input supply and the regulated output voltage. The dropout voltage will determine the minimum voltage required at the device's input to maintain regulation. For example, a 3.3 V linear regulator that has 1 V of dropout requires the input voltage to be at least 4.3 V. Linear regulators with dropout voltages below 600 mV belong to this low-dropout class, but typical dropout voltages are between 200 and 300 mV Typical standard linear regulators (HDOs) have voltage drops as high as 2 V which are acceptable for applications with large input-to-output voltage difference such as generating 2.5 V from a 5 V input. There are however some applications in which we have to generate an output of 3.3 V from a 3.6 V Li-Ion battery which means requiring a much lower dropout voltage (less than 300 mV). These applications require the use of this low-dropout to achieve this lower dropout voltage.

Figure 1. Typical Input-Output Voltage Characteristics of a Linear Regulator [2]
Figure 1 above illustrates the three regions of operation of a linear regulator: linear, dropout, and off regions [2].

Figure 2. Linear Regulator Functional Diagram [3]
A linear regulator operates by using a voltage-controlled current source to force a fixed voltage to appear at the regulator output terminal (see Fig. 2). The control circuitry must monitor (sense) the output voltage, and adjust the current source (as required by the load) to hold the output voltage at the desired value [3]. Figure 3 shows an LDO block diagram in its most basic form. The input voltage is applied to a pass element, which is typically an N-channel or P-channel MOSFET, but can also be an NPN or PNP transistor. The pass element operates in the linear region in order to drop the input voltage down to the desired output voltage. The resulting output voltage is then sensed by the error amplifier and compared to a reference voltage. In the figure, the two resistors shown are say 1 and 2 ( 1 is for the one connected to pass element's drain, and 2 is for the one connected to ground). The error amplifier drives the pass element's gate to the appropriate operating point to ensure that the output is at the correct voltage. As the operating current or input voltage changes, the error amplifier modulates the pass element (or more precisely the pass element's resistance) to maintain a constant output voltage.

Figure 3. Low Dropout Voltage Regulator Block Diagram [1]
Quintessential characteristic of a low-dropout regulator (LDO) thus has to be the dropout voltage. After all, that is the source of its name and acronym. Other than the dropout voltage, an LDO is also characterized by its quiescent current, load regulation, line regulation, maximum current (which is decided by the size of the pass transistor), speed (how fast it can respond as the load varies), voltage variations in the output because of sudden transients in the load current, output capacitor and its equivalent series resistance.

Building Blocks of a Low-Dropout Voltage Regulator
From the explanation of how the device works, a typical "linear" series voltage regulator (see again Fig. 3) thus consists of four main components. The first component is a reference voltage (shown as ). The second component is a mean for scaling the output voltage and comparing it to the reference (shown as the two scaling resistors, say 1 and 2 ). The third component is a feedback amplifier (shown as an error amplifier). One input of the error amplifier monitors the fraction of the output determined by the resistor ratio of 1 and 2 . The other input of this error amplifier comes from a stable voltage reference (a bandgap voltage reference will be used). Finally, the last component is a series pass transistor, which is a bipolar or a MOSFET (shown as a N-type MOSFET), whose voltage drop is controlled by the error amplifier to maintain the output voltage at the required value [8].

Voltage Reference
As stated above, one input of the error amplifier, the input (+), is a constant voltage produced by a voltage reference . This voltage reference will generate a stable voltage that is ideally independent of changes in temperature and other external factors. One way to achieve this stable voltage is by using a band-gap voltage reference.

Scaling the Output Voltage
This second part uses two resistors 1 and 2 to form a resistive feedback network, consisting of a voltage divider. It will provide a scaled output voltage. The magnitude of the scaled output voltage must be equal to the reference voltage .

Error Amplifier
The third part is an error amplifier. This error amplifier will constantly compares the reference voltage with the feedback voltage (voltage provided by the voltage divider).
An error amplifier configuration is the most widely used building block in analog integrated-circuit design. Error amplifier is most commonly encountered in feedback unidirectional voltage control circuits, where the sampled output voltage of the circuit under control (shown here as ), is fed back and compared to a stable reference voltage (shown here as ). Any difference between the two generates a compensating error voltage which tends to move the output voltage towards the design specification.

Series Pass Transistor
A MOS transistor is used for the pass transistor. Because a MOS transistor is an excellent switching device, it is possible to connect this transistor in series with a logical signal to either pass or inhibit the signal [9].
A MOS transistor connected in this way is called a pass transistor or transmision gate because it passes or transmits signals under control of its gate terminal. Hence its name. It is shown in Fig. 3 that the pass transistor will pass or inhibit a current pass through it from to (known as current).
In addition to passing or inhibit the signal, the other function of this series pass transistor is to create a voltage drop. This pass element transitor will operates in its linear region to drop the input voltage down to the desired output voltage.

More Details on Building Blocks
This section will explain in more detail about the various parts of a Low-Dropout Voltage Regulator

Reference Voltage
The voltage reference used here is an improved band-gap reference voltage, which is a temperature independent references voltage. Its concept is shown in Fig. 4 below.
The base-emitter voltage of a BJT transistor is a linear function of the absolute temperature and exhibits a temperature coefficient of about -2 mV/°C. If a voltage that is a linear function of the absolute temperature and has a positive temperature coefficient of also 2 mV/°C (i.e. +2 mV/°C) can be generated, then the variations introduced by the base-emitter junction may be able to be compensated for.

Figure 4. Illustrated Concept of Bandgap Voltage Reference [13]
It was recognized in 1964 that if two bipolar transistors operate at unequal current densities, then the difference between their baseemitter voltages is directly proportional to the absolute temperature (current density is defined as the ratio of the collector current, , and the saturation current, .

Scaling the Output Voltage
The magnitude of voltage at the input (+) of the error amplifier is the same as . Thus, the values of the voltage divider resistors 1 and 2 will adjust accordingly.

Series Pass Transistor
Most LDOs use an N-channel or P-channel FET pass element and can have dropout voltages with magnitude less than 100 mV.  Figure 5 that the Drain (D) is connected to , and the Source (S) is connected to ).

Figure 5. Series Pass Transistor [1]
Under steady state operating conditions, an LDO behaves like a simple resistor. For example, with the following operating conditions: = 5V, = 3.3V, and = 500 mA, the LDO pass device behaves like a 3.4 resistor. This equivalent resistance is determined by calculating the voltage drop across the LDO and dividing by the load current, as stated in equation (1): Under these specific application operating conditions, the LDO can be replaced by a 3.4 Ω resistor with no change in output voltage or output current (i.e. static operating condition).
In practical applications, however, operating conditions are never static (i.e. and are never constant); therefore, feedback is necessary to change the LDO's effective resistance to maintain a regulated output voltage. Look at the set of versus characteristics for an NMOS transistor in Fig. 6 below for the explanation.  Fig. 7, which shows the operating region of an LDO's N-channel pass element. It is shown in Fig. 7 that the y-axis is the drain current or (Drain current = load current, = ). The x-axis is where = -. The magnitude of -is the dropout voltage .
If the curve in Fig. 7 is noted, it shows that the range of operation is limited in the x-axis by the saturation region of the pass element (can be compared with the curve in Fig.  6), and limited in the y-axis by either the pass element's saturation region or by the IC's programmed current limit. In order to operate properly and maintain a regulated output voltage, the pass element must operate within the boundaries set by these two lines.

Figure 7. Operation Region of an LDO's N-channel FET Pass Element [1]
In the example above, the Drain-to-Source voltage of 1.7 V ( = -= 5V -3.3V = 1.7V) and the drain current of 500 mA will set the operating point at point "A." At this point, the LDO sets the pass element's Gate-to-Source voltage at 3 V to maintain regulation. A line drawn through the origin and point "A" represents the 3.4 Ω resistance.
Consider there is a change to the static conditions in the example above (now see Fig. 3 and Fig. 7) : first, if the load resistance decreases (which means an increase in load current ), the LDO must react to maintain regulation. If it doesn't react, the LDO will have a higher voltage drop across the pass element which causes the output voltage to fall out of regulation ( will be lower than the specification of 3.3 V). The LDO must decrease the pass element's resistance by increasing the gate-to source voltage on the FET, according to the following equation (2) for calculating : When the gate-to-source voltage increases, the operating point now moves upward, assuming a fixed input and output voltage (which means that will remain at 1.7 Volt).
If the increase in is such that now become 700 mA, the error amplifier has to increase the pass element's gate-to-source voltage to 3.5 V in order to maintain regulation. This corresponds to "B." A line drawn through the origin and point "B" now represents a pass element resistance of 2.4 Ω . Figure. 7 also shows that with a drain-to-source voltage of 1.7 V, the LDO's maximum current draw is only limited by the maximum programmed current limit.
Next, consider a decrease in input voltage (see again Fig.  7). In this case, the pass element must reduce its drain-tosource voltage to keep the output in regulation (note that = − , so if reduces then also reduced in order to maintain the value of ).
If is reduced to 4 V, the operating point now moves to point "C" ( = 4 V -3.3 V = 0.7 V). This point represents a 1Ω resistance ( Any further increase in current or decrease in input voltage forces the operating point onto the saturation line of the pass element (shown as a slope line labeled "Saturation line" at the curve of Fig. 7).

Error Amplifier (Differential Pair)
Differential amplifiers have become circuits that are very useful because of their compatibility with integrated circuit technology, together with their ability to amplify the differential signal. Their two inputs can be operated either as a common mode input voltage or as a differential input voltage. Figure 8 below shows the basic MOS differential-pair configuration. It consists of two matched transistors, 1 and 2 , whose sources are joined together and biased by a constant-current source I [10]. The two resistors labeled are the active loads. The active loads can actually consist of any circuits that will replace those two resistances. Thus, the active loads could be an n-channel active enhancement resistor load, a current source load, or a current mirror load. The last method (i.e. current mirror load) uses a current mirror to form the load devices. The advantage of this configuration is that the differential output signal is converted to a single ended output signal with no extra components required. The output is taken between one of the drains and ground rather than between the two drains and ground. Here, there is a conversion from differential to single-ended. This differential pair configuration built here makes use of this current mirror load configuration [9].
Shown at the bottom-middle of Fig. 8 is a constant current source I. This part is usually implemented by a MOSFET circuit of the type basic MOSFET constant-current source.

The Current-Mirror-Loaded MOS Differential Pair
An example of a current-mirror-loaded MOS differential pair configuration is shown in circuit diagram of Figure 9.
In that figure, the MOS differential pair is formed by transistors 1 and 2 , which is loaded by a current mirror formed by transistors 3 and 4 . Figure 9. The current-mirror-loaded MOS differential pair [10] To see how this circuit operates, consider first the quiescent or equilibrium state with the two input terminals connected to a dc voltage equal to the common-mode equilibrium value, in this case 0 V, as shown in Fig. 10. Figure 10. The circuit at equilibrium assuming perfect matching [10] Assuming perfect matching, the bias current I divides equally between 1 and 2 . The drain current of 1 , 2 , is fed to the input transistor of the mirror, 3 . Thus, a replica of this current is provided by the output transistor of the mirror, 4 . Observe that at the output node the two currents 2 balance each other out, leaving a zero current to flow out to the next stage or to a load (not shown). Further, if 4 is perfectly matched to 3 , its drain voltage will track the voltage at the drain of 3 ; thus in equilibrium the voltage at the output will be -3 .
An imbalance in the drain currents of 1 and 2 will cause the output of the diff-amp to swing either towards or towards ground. The minimum input common mode voltage is given by equation (3) where the minimum voltage across the current source is assumed to be , . The maximum input common mode voltage is determined knowing that the drain voltage of 2 is the same as the drain voltage of 1 (when both diff-amp inputs are the same potential), that is, -3 of the PMOS. We can therefore write equation (4) The voltage output swing can be determined by noting that the magnitude of maximum output voltage is limited by keeping 4 in saturation. Therefore, equation (5), The magnitude of minimum output voltage is determined by the voltage on the gate of 2 ( 2 must remain in saturation). As shown in equation (6).

Results of the Design
The design process for all of the building blocks of this Low Dropout Voltage Regulator was performed by using the Multisim Live Online Circuit Simulator.
Multisim Live Simulator allows users to take the same simulation technology used in academic institutions and industrial research today, and use it anywhere, anytime, on any device.
Multisim Live offers an intuitive schematic layout experience in a web browser. With the familiar Multisim interface, component library and interactive features ensures we can capture our design with no difficulty.
This tool also allows for testing the behavior of a circuit, demonstrate the application of a design, or illustrate concepts to students. With Multisim Live, we can easily share interactive simulations with no need to install any application software [11].
The incoming sub-sections shows the design of each of building block of this LDO by using the Multisim Live Simulator.

Improved Bandgap Reference Voltage
To compensate the variations introduced by the baseemitter junction, a thermal voltage is used. Thermal voltage ( ) given by the following equation is a linear function of the absolute temperature, equation (7): where k is the Boltzmann constant, q is the charge carried by a single electron, and T is temperature in Kelvin. Thus, temperature coefficient of the thermal voltage is of magnitude ≅ +0.085 ° . This temperature coefficient is positive but it is much less than the desired value of +2 °.
To solve this problem, the temperature coefficient of thermal voltage was amplified by a temperature independent constant such that is equal to about 2 ° . The temperature independent constant needed is therefore 2 0:085 mV = 23.5.
In Fig. 4, it is shown that the thermal voltage is produced by a" generator" block. When the output of the thermal voltage is multiplied by temperature independent constant and then added to the BE(on) , a reference voltage is obtained given by the following expression (8): At ambient room temperature of 300 °K, equation (8) will produce a reference voltage of 1.26 V assuming ( ) is 0.65 V. That is, 1.26 V ≅ 0.65 + 23.5(0.000085 × 300) .
Practical realizations of band-gap references in bipolar technologies can take on several forms. One form is illustrated in Fig. 11. It is a self-biased band-gap reference circuit. This improved band-gap is developed using an opamp. The advantage of the op-amp is to remove the dependence of the currents upon the power supply. The method by which this is done is to force the relationship ) Equation (11) shows that the voltage is generated by the difference between two base-emiter drops (band-gap references usually use the difference of two BJTs to create the " generator" block in Fig. 4).
Since the same current that flows in 3 also flows in 2 , the voltage across 2 must be 2 = 2 2 = 3 2 = 3 ) Equation (12) shows that 2 , the voltage across 2 , is proportional to absolute temperature (PTAT) because of the temperature dependence of the thermal voltage . Since the op amp forces the voltages across 1 and 2 to be equal, the currents 1 and 2 are both proportional to temperature if the resistors have zero temperature coefficient. , 24, (1), JANUARI 2022  p-ISSN 1411-0814 e-ISSN

Figure 12. Result of the Improved Band-gap Voltage Reference
The design result of the Improved Band-gap Voltage Reference is shown in Fig. 12 above. Resistors with values of 2 = 1 = 10.2 kΩ and 3 = 1 kΩ are used. It is shown in those figure the magnitude of the currents that pass through 2 dan 1 , and also the voltage produced. A voltage of approximately 1.30 V is produced. This is the voltage that will be fed to the input (+) of the error amplifier (see Fig. 3).

Scaling the Output Voltage
The circuit that is used to feedback the output voltage can be represented by Fig. 13 below It can be seen that the circuit is a basic op amp circuit of type non-inverting amplifier [12]. The input-output relation of a non-inverting amplifier circuit can be expressed using the following expression.
Using the components in the circuit of Fig. 13 above, in the equation is then substituted for , 2 is substituted for 1 , and 1 is substituted for , which gives If for example, the regulator is to give an output of magnitude 3.0 V and the reference voltage produced by the bandgap voltage reference is of magnitude 1.30 V, so the ratio between 1 resistor and 2 resistor will be ( and of magnitude 4 kΩ for 2 therefore can be used.

Error Amplifier
The implementation of an error amplifier by using Nchannel MOSFET is shown in Fig. 14 below [13]. The circuit shown is a general circuit. First, the transistors labeled 1 and 2 form the basic MOS differential-pair configuration. These transistors are two matched transistors, whose sources are joined together.
Next, the two transistors labeled 3 and 4 form active loads that will replace the resistances in Fig. 8. It is shown that the active resistors are implemented by simply connecting the gate of p-channel enhancement MOS device to the drain. The sources of the p-channel devices are taken to the most positive voltage to eliminate the bulk effect. Therefore, the sources are connected to . This two p-channel configuration form a p-channel current mirror configuration. Hence the circuit is called a MOS differential amplifier with a current mirror load [9].

Figure 14. Differential-single-ended Conversion Error
Amplifier [13] The last two transistors labeled 5 and 6 form the basic MOSFET constant-current source which is used for biasing the MOS differential-pair configuration. The can be related to the reference current as follows The two inputs of the MOS differential pair configuration are shown as the inputs labeled 1 and 2 which will come from the feedback circuit and the voltage reference , respectively.
Because this is a differential amplifier with a current mirror load, the differential output signal is converted to a single ended output signal. It is shown that the differential output signal is which is taken from the drains of 4 and 2 . This is voltage that will drive the pass element's gate to the appropriate operating point to ensure that the output is at the correct voltage. Fig. 15 below is the result of the n-channel input differential amplifier. The two inputs are 1 and 2 . The differential input is = 2 -1 . The output voltage is .

Figure 15. Multisim Live Design Result of the Differentialsingle-ended conversion Error Amplifier
The circuit was constructed using components with component's parameters shown in the following Table 1. First, the circuit was arranged with both of the input 1 and 1 were set to 1.30 V. This is approximately the same as magnitude of the reference voltage . When the simulation was run, an output voltage of magnitude 3.9000 Volt was obtained. (This is the voltage that would be fed to the pass element transistor when output voltage from the pass element has a magnitude of 3.0 V).
With of 5 V, from (5) the output can swing up to 5 V minus 450 mV = 4.55 V before 4 triodes. Then from (6), the output can swing down to 1.3 V minus 500 mV = 800 mV before 2 triodes.
The setting was then changed by increasing and lowering the magnitude of the voltage at the 2 input while keeping the gate of 1 (the input at 1 ) at 1.30 Volt. First, the voltage at 2 was increased up to 1.35 V. When the simulation was run, it was shown that the voltage at was 681.71 mV. Next, we decreased the voltage at 2 down to 1.25 V. When the simulation was run, a voltage of magnitude 4.6230 V was obtained at .
The variation of output voltage of this error amplifier will be useful when there is a change in the load resistance of the LDO (i.e. which means change in load current). When this happens, the system must react by changing the pass element's resistance. This is done by changing of that pass element by changing gate voltage of that pass element.

Series Pass Transistor
The specification of the Low-Dropout regulator built here is that it has a worst-case dropout voltage (maximum dropout voltage) of 200 mV at 200 mA load current for a 3.0 V output. Figure 16 below is the series pass transistor.
To conform with the above specification, a load current (= ) = 200 is used for the test condition, which means that this series pass transistor will operate at = 200 mA.

Figure 16. A Series Pass Element
To determine the value required for , the voltage at the source terminal of this pass element need to be known first. The voltage at the source terminal is The saturation line equation (see Fig. 6 and Fig. 7) will be used to obtain magnitude of the process transconductance parameter and the transistor aspect ratio for the series pass transistor. Thus, for the specification worst-case dropout voltage (maximum dropout voltage) of 200 mV, means that ( ) = 200 . The equation for is as follows: By looking at Fig. 6, the boundary between the triode and the saturation regions, that is, the locus of the saturation points, is a parabolic curve described by By substituting the value of with 200 mA = 0.2 A, and substitute the value of ( ) with 200 mV = 0.2 V, will give an expression

= ( )
Equation (19) can be satisfied if a process transconductance parameter = 4 2 (for example), and a transistor aspect ratio of magnitude 2.5 were used. Hence, the series pass transistor was shown with such parameters shown in Fig. 16.
Furthermore, the magnitude of can be determined from ( ) by using the following expression Note that a setting ℎ ℎ of 700 mV = 0.7 V was used. The magnitude of overdrive voltage = With the specification to create a of 3.0 V, this pass element transistor thus will be operated with a gate voltage of 3.9 V as shown in Fig. 16.
Now, for example there is an application that requires = 3 V at 170 mA with an input voltage that varies between 3.15 V and 3.45 V. Using this regulator, the actual magnitude of dropout will be less than 200 mV since the load current is 170 mA (less than 200 mA). The curve of Fig. 17 below can be used, which shows an example of output voltage vs. input voltage characteristic of an LDO. Note that with less load current , less dropout voltage will be obtained [14].

Figure 17. The Output Voltage vs. Input Voltage Characteristics of an LDO [14]
For the pass element transistor designed here, the results of changing load current are shown in the following Table 2.
The single ended error amplifier circuit in section immediately above was then connected to the gate of this series pass transistor. The general circuit of which is shown in Fig. 18 below. Here, note the connection between the common-source amplifier, 5 , (act as the series pass transistor), to the output of the diff-amp in Fig. 15. When the inputs to the diff-amp are at the same potential, the currents that flow in 3 and 4 are equal (= 1 2 ). The drain of 3 is then at the same potential as its gate. This means, for biasing purposes, that the gate of 5 can be treated as if it were tied to the gate of 4 ( 3 ). Thus, 5 are now being biased from the Current Mirror Load [15]. In this design, a ℎ ℎ setting of 0.3 Volt was used for the pass element.

Figure 18. Using an Error Amplifier to Bias a Next Stage Circuit
The overall design result of this connection between the error amplifier and the transistor pass element can be seen at Fig. 19. It is shown in those figure, the pass element was set with channel width W = 10 and channel length L = 4 , so resulting in a transistor aspect ratio = 2.5.
At the simulation, the following results were obtained. At the beginning, when the load in series with the series pass transistor was of magnitude 15.0 Ω, a load current of 200 mA was obtained, and the voltage at the source terminal of the series pass transistor was of magnitude 3.0000 V. At the gate of the pass transistor, a voltage of 3.9001 V was obtained. The gate to source voltage is equal to 0.9001 V.
Next, consider there is a change to the static operating condition when there is a decreasing load resistance (i.e. which mean an increase in load current). For example, when the series load was changed to 10 Ω, a load current of 300 mA was obtained (not 200 mA anymore). The voltage at the gate terminal of the pass transistor is now 3.9451 V. This new gate's voltage maintains the voltage at the source terminal of the pass transistor at 3.0 V. The gate to source voltage is now increase to 0.9451 Volt.

Figure 19. Series Pass Transistor Biased with an Error Amplifier
The same also applies when the load resistance increases. For example, when the series load resistance was changed to 20 Ω, a load current of 150.00 mA was obtained. The voltage at the gate terminal of the pass transistor is now 3.8734 V. This new gate's voltage maintains the voltage at the source terminal of the pass transistor at 3.0 V. The gate to source voltage is now decrease to 0.8734 Volt. For the other results obtained for varying the load current are tabulated in Table 3. Now, consider a decrease in input voltage . This time, the pass element transistor must reduce its drain-to-source voltage in order to keep the output stay in regulation.
Consider first when the load current is at magnitude 200 mA. The experiment was started with of 6 V and then slowly reduce it. It turns out that the load current remains at 200 mA and the output remains at 3.0000 V, until reach 4.30 V. When is less than 4.30 V, the load current and the output voltage begin to drop. Next, other magnitude of the load current (less load current) were used and different results were obtained. The results of reducing at various load currents were tabulated in Table 4. With the NMOS pass element transistor, as approaches ( ) the error amplifier will increase in order to lower the and maintain regulation. This presents a problem though, because as continues to approaches ( ) , the output voltage from error amplifier (i.e. the gate voltage of the pass transistor, ) will also decrease, instead of increase. This is because the PMOS transistor of error-amplifier, 4 , will saturate (remember that ( ) of those 4 is 450 mV). This prevents ultralow dropout.
In order to get a lower dropout voltage, the NMOS pass element transistor was replaced with a PMOS one. Figure  20 below shows a PMOS LDO architecture (as opposed to the NMOS LDO shown in Fig. 13). In order to regulate the desired output voltage, the feedback loop controls the drain-to-source resistance, or . As approaches ( ) , the error amplifier will drive the gate-tosource voltage, , more negative in order to lower and maintain regulation [16].

Figure 20. Low Dropout with PMOS Series Pass Transistor [16]
The Multisim circuit for the PMOS LDO architecture was shown in Fig. 21.
With those PMOS pass element, results as shown in Table  5 were obtained when the battery input reduced approaching the output voltage nominal. The results were shown with a load current of 200 mA. It is shown that a dropout voltage, , of magnitude 200 mV was obtained at 200 mA load current. This dropout voltage is much lower than the previous one when using an NMOS pass element. This PMOS LDO regulator begins dropping out at 3.19 V input voltage.  For results with other magnitude of load currents can be seen in Table 6. It is shown by those table that at smaller load currents, the dropout voltage is proportionately lower. Next, shown in Table 7 are the results obtained when there are changes in load current. The results were shown for a battery voltage of 5 Volt Then, Table 8 shows the results of DC Line Regulation of this LDO in connection with the result of Table 6 and  Table 7. DC line regulation is a measure of the circuit's ability to maintain the specified output voltage under varying input voltage. DC line regulation is defined as ∆ ∆ . Results in Table 8 above shows that the line regulation gets worse as the load current increases. . It is shown in Table 9 that when the load current increases, the PMOS pass element must decrease its resistance, , by increasing its the source-to-gate voltage . Increasing is done by lowering its gate voltage. However, there is a minimum limit for this pass element's gate voltage. The magnitude of this minimum voltage is determined by keeping in mind that the transistor 2 must remain in saturation.
From the table, it can be seen that the load regulation of this LDO is of magnitude

Discussions
Some discussion about the design of this low-dropout voltage regulator can be stated as follows.
An LDO is characterized by its drop-out voltage, quiescent current, load regulation, line regulation, maximum current (which is decided by the size of the pass transistor), speed (how fast it can respond as the load varies), voltage variations in the output because of sudden transients in the load current, output capacitor and its equivalent series resistance.
From the various results of simulation above, some points can be discussed as follows in connection with some of the LDO characteristics 1. Dropout voltage is the input-to-output differential voltage at which the circuit ceases to regulate against further reductions in input voltage; this point occurs when the input voltage approaches the output voltage.
The dropout voltage of this voltage regulator designed here is of magnitude 200 mV at load current of 200 mA. It was also shown that at smaller load currents, the dropout voltage is proportionately lower.

Conclusions
From this research, it can be concluded that a standard Low Drop Out (LDO) can be built from four parts, which are a reference voltage, a circuit for scaling the output voltage, an error amplifier, and a series pass transistor. A low dropout voltage can be obtained by using a PMOS for the pass element. Quiescent current, DC load regulation, and DC line regulation can be inferred from the experiment results.