DOI: https://doi.org/10.14710/transmisi.24.1.9-22

DESIGN AND SIMULATION OF BUILDING BLOCKS OF A LOW-DROPOUT VOLTAGE REGULATOR

*Arief Wisnu Wardhana orcid  -  Departemen Teknik Elektro, Fakultas Teknik, Universitas Jenderal Soedirman, Indonesia
Azis Wisnu Widhi Nugraha  -  Departemen Teknik Elektro, Fakultas Teknik, Universitas Jenderal Soedirman, Indonesia
Eko Atmojo  -  Departemen Teknik Elektro, Fakultas Teknik, Universitas Jenderal Soedirman, Indonesia
Ari Fadli  -  Departemen Teknik Elektro, Fakultas Teknik, Universitas Jenderal Soedirman, Indonesia
Dikirim: 12 Nov 2021; Diterbitkan: 3 Peb 2022.
Akses Terbuka Copyright (c) 2022 Transmisi: Jurnal Ilmiah Teknik Elektro under http://creativecommons.org/licenses/by-sa/4.0.

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Low dropout regulators (LDOs) are a simple and inexpensive way to regulate an output voltage that is powered from a higher voltage input [1]. An LDO regulator is a DC linear voltage regulator that can regulate the magnitude of the output voltage even when the supply voltage is very close to the output voltage. In this research paper, various building blocks of a CMOS-based low-dropout voltage regulator were designed and simulated using Multisim LIVE, an online circuit simulator. All of the building blocks were then combined to form the device. Based on the results of the simulation, several spesifications of the LDO were determined. Those are the LDO’s dropout voltage, its quiescent current, its load regulation, and its line regulation. At the end of the design process, during testing it can be shown that this LDO resulted in a dropout voltage of magnitude 200 mV at 200 mA load current which is quite a low dropout voltage. The design has a quiescent current of magnitude 300 , a load regulation of magnitude ,  and a line regulation of magnitude .

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Kata Kunci: regulator tegangan, tegangan dropout, arus quiescent, regulasi beban, regulasi line

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Bahasa : EN
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